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authorAugustin Fabre <augustin@augfab.fr>2019-12-29 14:29:25 +0100
committerAugustin Fabre <augustin@augfab.fr>2019-12-29 15:38:40 +0100
commit653c12e1bb314f07b6a1a38b15b5ab2f2a5c9a32 (patch)
tree56b615712f0434cddd6131c535681b209453c248
parent8f32687c3e7ebce77e9b238795e6dfbea3a8b4ec (diff)
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Remove useless begin..end
-rw-r--r--logical/cpu.sv12
1 files changed, 4 insertions, 8 deletions
diff --git a/logical/cpu.sv b/logical/cpu.sv
index 06645d0..2498437 100644
--- a/logical/cpu.sv
+++ b/logical/cpu.sv
@@ -54,18 +54,14 @@ always @(posedge clk_i or negedge nrst_i) begin
addr_q <= addr;
we_q <= '0;
case (op)
- NOR: begin
+ NOR:
state_q <= READ_NOR;
- end
- ADD: begin
+ ADD:
state_q <= READ_ADD;
- end
- STA: begin
+ STA:
state_q <= WRITE;
- end
- JCC: begin
+ JCC:
state_q <= carry ? FETCH : CLEAR_CARRY;
- end
default: begin
end
endcase