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authorAugustin Fabre <augustin@augfab.fr>2019-12-29 14:28:26 +0100
committerAugustin Fabre <augustin@augfab.fr>2019-12-29 15:38:16 +0100
commit8f32687c3e7ebce77e9b238795e6dfbea3a8b4ec (patch)
treebc46c171cbb76692865e5913bc9e16467098c4f5
parent44d2a99e55373d696ce362355f9d1c9e2499956c (diff)
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Propagate X
-rw-r--r--logical/cpu.sv5
1 files changed, 1 insertions, 4 deletions
diff --git a/logical/cpu.sv b/logical/cpu.sv
index c738b06..06645d0 100644
--- a/logical/cpu.sv
+++ b/logical/cpu.sv
@@ -64,10 +64,7 @@ always @(posedge clk_i or negedge nrst_i) begin
state_q <= WRITE;
end
JCC: begin
- if (carry)
- state_q <= FETCH;
- else
- state_q <= CLEAR_CARRY;
+ state_q <= carry ? FETCH : CLEAR_CARRY;
end
default: begin
end